HAND-WRITTEN NUMBER RECOGNITION BASEDCNN USING VERILOG



Authors

  • R. Rajakumar, Dr. Kumar Keshamoni

DOI:

https://doi.org/10.15282/jmes.17.1.2023.10.0759


Keywords:

Convolution Neural Networks (CNNs), VERILOG, FPGA, Hand-written number recognition


Abstract

Convolutional Neural Networks (CNNs) have emerged as a cornerstone in computer vision, proving instrumental in diverse applications like image and video classification, recommender systems, and natural language processing. These networks draw inspiration from the intricate connectivity patterns found in the visual cortex of animals. Despite their success, CNNs face significant challenges during training, including extensive computational costs and substantial storage requirements.In order to mitigate these challenges, this study focuses on optimizing relevant data within the CNN model by incorporating a lifting method. This approach aims to strike a balance between data size and computational efficiency. The paper proposes a novel FPGA-based handwriting recognition system that employs a CNN algorithm for recognizing MNIST digital sets. The hardware design encompasses key techniques such as image cropping, convolution, activation functions, pooling, pipeline processing, and parallel processing of multiple convolution kernels. Taking advantage of the parallel computing capabilities inherent in hardware circuits, the proposed MNIST detection system demonstrates accelerated processing speeds. The architecture is meticulously crafted using Verilog HDL and implemented on the Altera DE2 FPGA development board. The paper provides detailed insights into hardware design strategies, emphasizing image processing stages like cropping, convolution, activation functions, pooling, and the concurrent processing of multiple convolution kernels. This work contributes to the field by presenting a VLSI implementation of a hand-written number recognition system based on CNNs. The system's performance is comprehensively characterized in terms of classification accuracy, area utilization, processing speed, and power consumption. The innovative hardware design techniques showcased in this research not only enhance the efficiency of the MNIST detection system but also pave the way for advancements in real-time image recognition applications.



Published

2023-05-10

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